The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to structures for a field-effect transistor and methods of forming a structure for field-effect transistor.
Device structures for a field-effect transistor generally include a body region, a source and a drain defined in the body region, and a gate structure configured to apply a control voltage that switches carrier flow in a channel formed in the body region. When a control voltage that is greater than a designated threshold voltage is applied, carrier flow occurs in the channel between the source and drain to produce a device output current.
Contacts may provide vertical electrical connections to features of semiconductor devices, such as the gate structure and source/drain regions of a field-effect transistor. Self-aligned contacts (SAC) are formed in contact openings that are constrained during etching by the configuration of adjacent structures, e.g., sidewall spacers on adjacent gate structures, as opposed to being constrained by a patterned resist. For example, a self-aligned contact may be formed in a contact opening that is defined by selectively etching one material, e.g., silicon dioxide, of an interlayer dielectric layer relative to other materials, such as silicon nitride caps on adjacent gate structures. To avoid yield loss, the silicon nitride caps should effectively electrically isolate the metal gate of the gate structure from the self-aligned contacts. However, in conventional arrangements, the proximity of the conformal layers of the metal gate to the self-aligned contact provides a significant risk of shorting.
Improved structures for a field-effect transistor and methods of forming a structure for field-effect transistor are needed.